1 ps8609b 11/12/08 features ? maximum rated frequency: 133 mhz ? low cycle-to-cycle jitter ? input to output delay, less than 200ps ? external feedback pin allows outputs to be synchronized to the clock input ? 5v tolerant input* ? operates at 3.3v v dd ? test mode allows bypass of the pll for system testing purposes (e.g., ibis measurements) ? space-saving packaging (pb-free and green available): ? 8-pin, 150-mil soic (w) description the pi6c2404a-1 is a pll-based, zero-delay buffer, with the ability to distribute four outputs of up to 133 mhz at 3.3v. two banks of two outputs exist, outa[1?2] and outb[1?2]. an external feedback pin is used to synchronize the outputs to the input; the relationship between loading of this signal and the other outputs determines the input-output delay. the pi6c2404a-1 is characterized for both commercial and industrial operation. block diagram pin configuration 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 zero-delay clock buffer pi6c2404a-1 * fb_in and clkin must reference the same voltage thresh- olds for the pll to deliver zero delay skewing 1 2 3 gnd 4 outa2 fb_in outb2 outb1 8 7 6 5 clkin outa1 v dd 8-pin w ni pl angi sn oitpircsed 1n iklc )nwod-llupkaew(ycneuqerfecnereferkcolctupni 3, 2] 2-1[atu oa knab,tuptuokcolc 7v dd ylppusv3.3 4d n gd nuorg 6, 5] 2-1[btu ob knab,tuptuokcolc 8n i_b ft upnikcabdeefllp pin description pll clkin fb_in outa1 outa2 outb2 outb1 08-0298
2 ps8609b 11/12/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c2404a-1 zero-delay clock buffer the relationship between loading of the fb_in signal and other outputs determines the input-output delay. zero delay is achieved when all outputs, including feedback, are loaded equally. zero-delay and skew control clkin input to output bank delay vs. difference in loading between fb_in pin and outa/outb pins maximum ratings supply voltage to ground potential ............................................................................................. ................................ ?0.5v to +7.0v dc input voltage (except clkin) ........................................................................................................................ ?0.5v to v dd +0.5v dc input voltage clkin ......................................................................................................... ............................................. ?0.5 to 7v storage temperature ............................................................................................................ ....................................... ?65oc to +150oc maximum soldering temperature (10 seconds) ........................................................................................................................... 260oc junction temperature .................................................................................................................................................................. 150oc static discharge voltage (per mil-std-883, method 3015) ........................................................................ ............................ >2000v 600 800 400 200 0 C200 C400 C600 C800 C900 C1000 C25 C20 C15 C10 C5 0 5 10 15 20 25 output load difference: fb_in load - outa/outb load (pf) clkin - input to outa/outb delay (ps) pi6c2404a-1 retemara pn oitpircse d. ni m. xa ms tinu v dd egatlovylppu s0 . 36 . 3v t a erutarepmetgnitarepolaciremmo c0 0 7 co erutarepmetgnitarepolairtsudn i0 4 ?5 8 c l zhm001woleb,ecnaticapacdaol ? 03 fp zhm331otzhm001morf,ecnaticapacdaol ? 51 c ni ecnaticapactupni ? 3.7 operating conditions (v cc = 3.3v 0.3v) 08-0298
3 ps8609b 11/12/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c2404a-1 zero-delay clock buffer notes: 1. clkin and fb_in inputs have a threshhold voltage of v dd /2. sretemara pe ma ns noitidnoctse t. ni m. py t. xa ms tinu f o ycneuqerftuptuo daolfp03 01 001 zhm daolfp5 13 31 t cd elcycytud )1( vtaderusaem dd f,2/ tuo daolfp03zhm76.66 <0 4 05 06 % vtaderusaem dd f,2/ tuo daolfp51zhm05 <5 45 5 t r emitesir )1( daolfp03,v0.2dnav8.0neewtebderusae m2 .2 sn daolfp51,v0.2dnav8.0neewtebderusae m5 .1 t f emitllaf )1( daolfp03,v0.2dnav8.0neewtebderusae m2 .2 daolfp51,v0.2dnav8.0neewtebderusae m5 .1 t )o(ks wekstuptuoottuptuo knabemasnihtiw )1( dedaolyllauqestuptuolla 002 sp weksbtuootatuo )1( t 0 egdegnisirniklc,yaled egdegnisirni_bfot )1( vtaderusaem dd 2/ 572 t )d(ks weksecived-ot-ecived )1( vtaderusaem dd secivedfosnipni_bfno2 /00 05 t tij rettijelcyc-ot-elcyc )1( daolfp03dedaol,zhm76.66taderusae m0 02 sp daolfp51dedaol,zhm331taderusae m0 51 t kcol emitkcolllp )1( skcolcdilav,ylppusrewopelbats snipni_bfdnaniklcnodetneserp 0. 1s m ac electrical characteristics for industrial temperature devices dc electrical characteristics for industrial temperature devices retemara pn oitpircse ds noitidnoctse t. ni m. xa ms tinu v li egatlovwoltupni 8.0 v v hi egatlovhgihtupni 0.2 i li tnerrucwoltupn iv ni =v 00 5 a i hi tnerruchgihtupn iv ni =v dd 211 v lo egatlovwoltuptu oi lo am8 =4 .0 v v ho egatlovhgihtuptu oi ho am8? =4 .2 i dd tnerrucylppus vtastupnitceles,zhm001stuptuodedaolnu dd dngr o4 5 am niklc,zhm66stuptuodedaoln u9 3 niklc,zhm33stuptuodedaoln u2 2 08-0298
4 ps8609b 11/12/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c2404a-1 zero-delay clock buffer notes: 1. clkin and fb_in inputs have a threshhold voltage of v dd /2. 2. t dc = t high t high + t low sretemara pe ma ns noitidnoctse t. ni m. py t. xa ms tinu f o ycneuqerftuptuo daolfp03 01 001 zhm ,daolfp5 13 31 t cd elcycytud )2( vtaderusaem dd f,2/ o daolfp03,zhm76.66 <0 40 50 6 % vtaderusaem dd f,2/ o daolfp51,zhm05 <5 40 55 5 t r emitesir )1( fp03@ v0.2dnav8.0neewtebderusaem 2.2 sn emitesir )1( fp51@ 5.1 t f emitllaf )1( fp03@ 2.2 emitllaf )1( fp51@ 5.1 t )o(ks wekstuptuoottuptuo )1( knabemasnihtiw v,dedaolyllauqestuptuolla dd 2 /0 02 sp weksbtuootatuo )1( v,dedaolyllauqestuptuolla dd 2 /0 02 t 0 niklc,yaledtuptuoottupni gnisirni_bfotegdegnisir egde )1( vtaderusaem dd 2 /5 72 t )d(ks weksecivedotecived )1( vtaderusaem dd secivedfosnipni_bfno2 /00 05 t tij rettijelcyc-ot-elcyc )1( stuptuofp03dedaol,zhm76.66taderusae m0 02 stuptuofp51dedaol,zhm331taderusae m0 51 t kcol emitkcolllp )1( skcolcdilav,ylppusrewopelbats snipni_bfdnaniklcnodetneserp 0. 1s m ac electrial characteristics for commercial temperature device dc electrical characteristics for commercial temperature devices retemara pn oitpircse ds noitidnoctse t. ni m. xa ms tinu v li egatlovwoltupni ? 8.0 v v hi egatlovhgihtupni 0.2 ? i li tnerrucwoltupn iv ni =v 0 ? 05 a i hi tnerruchgihtupn iv ni =v dd ? 211 v lo egatlovwoltuptu oi lo am8= ? 4.0 v v ho egatlovhgihtuptu oi ho am8? =4 .2 ? i dd tnerrucylppu sv @stupnitceleszhm001stuptuodedaolnu dd dngro ? 45 i dd tnerrucylppu sv tastupnitceles,zhm76.66,stuptuodedaolnu dd dngro ? 9 3a m 08-0298
5 ps8609b 11/12/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c2404a-1 zero-delay clock buffer switching waveforms test circuit t low t high v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 t f t r 0.8v 2.0v 0.8v 2.0v output 0v 3.3v t sk(o) t sk(d) output output t 0 input fb_in fb_in device 1 fb_in device 2 duty cycle timing all outputs rise/fall time output-output skew input-output propagation delay device-device skew v dd c load v dd gnd gnd clk out outputs 0.1f 0.1f test circuit for all parameters 08-0298
6 ps8609b 11/12/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c2404a-1 zero-delay clock buffer packaging mechanical: 8-pin soic (w) pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com edocgniredr oe docegakca pn oitpircsedegakca pe gnargnitarepo ew1-a4042c6i pw neergdnaeerf-bp cioslim-051nip-8 laicremmoc eiw1-a4042c6i pw neergdnaeerf-bp cioslim-051nip-8 lairtsudni ordering information 1 .0040 .0098 seating plane .013 .020 .050 bsc .016 .0075 .0098 1 8 .0099 .0196 ? .050 .149 .157 x.xx x.xx denotes dimensions in millimeters 3.78 3.99 .189 .196 4.80 5.00 1.27 .016 .026 1.35 1.75 .2284 .2440 5.80 6.20 0.406 0.660 0.330 0.508 0.10 0.25 0.40 1.27 0.19 0.25 0.25 0.50 [ ? .053 .068 ref description: 8-pin, 150-mil wide, soic package code: w document control no. pd - 1001 revision: f date: 03/09/05 notes: 1) controlling dimensions in millimeters. 2) ref: jedec ms-012d/aa pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com notes: 1. thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. x = tape/reel 3. e = pb-free & green 08-0298
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